1. Field of the Invention
The present invention generally relates to non-volatile semiconductor memory devices, and more particularly, to a non-volatile semiconductor memory device comprising a plurality of memory blocks in which electrically erasable and writable non-volatile memory cells are arranged, the device having a function of collectively erasing memory blocks selected as erase object memory blocks. The present invention also relates to a method of performing an erasing operation in such a non-volatile semiconductor memory device.
In an erasing operation mode, such a non-volatile semiconductor memory device starts an erasing operation upon receipt of a first memory block address signal and an erase command signal from an address and command signal transmitter. After a timeout period comes to an end, an erasing operation is collectively performed for memory blocks selected as erase object memory blocks.
2. Description of the Related Art
FIG. 1 is a block circuit diagram showing the structure of an example of a non-volatile semiconductor memory device of the prior art. In this figure, reference numeral 1 indicates the non-volatile semiconductor memory device, reference numerals 2-0, 2-1, and 2-n indicate memory blocks each having electrically erasable and writable non-volatile memory cells, such as flash memory. Memory blocks 2-2 to 2-(n-1) existing between the memory blocks 2-1 and 2-n are not shown in the figure. Reference numeral 3 indicates an address latch circuit which latches a memory block address signal supplied from an address and command signal transmitter such as CPU. Reference numeral 4 indicates a block decoder which decodes the memory block address signal latched by the address latch circuit 3 so as to select memory blocks to be designated as erase object memory blocks by the memory block address signal.
Reference numerals 5-0, 5-1, and 5-n indicate block latch circuits corresponding to the memory blocks 2-0, 2-1, and 2-n, respectively. Each of the block latch circuits latches information on whether each corresponding memory block has been selected as an erase object memory block. Block latch circuits 5-2 to 5-(n-1) corresponding to the memory blocks 2-2 to 2-(n-1) are not shown in this figure.
Reference numeral 6 indicates a timer which outputs "1" before a start-up, and outputs "0" during the timeout period when started or reset. After the timeout period comes to an end, the timer 6 again outputs "1". Reference numeral 7 indicates a control circuit which receives an erase command signal, a write enable signal /WE, and a chip enable signal /CE, and which controls a latching process of the erase command signal, the address latch circuit 3, and the timer 6. The control circuit 7 controls the address latch circuit 3 to latch a memory block address signal at the timing of falling of the write enable signal /WE or the chip enable signal /CE, whichever is the later signal. The control circuit 7 also latches an erase command signal and starts or resets the timer 6 at the timing of rising of the write enable signal /WE or the chip enable signal /CE, whichever is the earlier signal.
In the above conventional non-volatile semiconductor memory device in the erasing operation mode, an erasing operation is collectively performed for memory blocks selected by the block decoder 4 and selected as erase object memory blocks by the block latch circuits 5-0 to 5-n.
FIG. 2 is a timing chart of an example operation of the conventional non-volatile semiconductor memory device of FIG. 1 in an erasing operation mode. In this example operation, the CPU first supplies a memory block address signal for designating the memory block 2-0. After the chip enable signal /CE falls, the write enable signal /WE falls. Here, the address latch circuit 3 latches the memory block address signal for designating the memory block 2-0 at a timing T1 when the write enable signal /WE falls. The block decoder 4 then decodes the memory block address signal latched by the address latch circuit 3 so as to select the memory block 2-0 as an erase object block memory. The block latch circuit 5-0 latches "0" as the information indicating that the memory block 2-0 has been selected. The control circuit 7 then latches an erase command signal (30H) and starts the timer 6 at a timing T2 when the write enable signal /WE rises. As a result, the output S6 of the timer 6 changes from "1" to "0", notifying the CPU that a timeout period during which an additional memory block address signal and an erase command signal can be inputted has started.
The memory block address signal for designating the memory block 2-0 is then followed by a memory block address signal for designating the memory block 2-1 as an erase object memory block, together with an erase command signal. The address latch circuit 3 latches the memory block address signal for designating the memory block 2-1 at a timing T3 when the write enable signal /WE falls. The block decoder 4 decodes the memory block address signal latched by the address latch circuit 3 so as to select the memory block 2-1 as an erase object memory block. The block latch circuit 5-1 latches "0" as the information indicating that the memory block 2-1 has been selected. The control circuit 7 then latches an erase command signal and resets the timer 6 at a timing T4 when the write enable signal /WE rises, thereby updating the timeout period. Thereafter, every time a memory block address signal and an erase command signal are supplied from the CPU during the timeout period, the latching of the memory block address signal and the erase command signal, and the resetting of the timer 6 are repeated. When the timeout period comes to an end, an erasing operation is collectively performed for the memory blocks selected as the erase object memory blocks.
FIG. 3 shows an example operation of the CPU which transmits address signals and command signals in the non-volatile semiconductor memory device of FIG. 1 in the erasing operation mode. It should be understood here that a step S8-5 is an operation by the non-volatile semiconductor memory device.
In the erasing operation mode, the CPU first supplies a memory block address signal and an erase command signal to the non-volatile semiconductor device, thereby performing a first memory block address and erase command writing operation in a step S8-1. When the control circuit 7 latches the erase command signal, the timer 6 is started, indicating that the timeout period, during which an additional memory block address and erase command writing operation can be performed, has started. If there is an additional memory block address, the CPU judges whether it is during the timeout period or not in a step S8-2. If it is during the timeout period, the CPU supplies the additional memory block address signal and the erase command signal to the non-volatile semiconductor memory device, thereby performing the additional memory block address and erase command writing operation in a step S8-3. Here, the CPU judges whether there is an additional memory block or not in a step S8-4. As long as there is an additional memory block, the steps S8-2 and S8-3 are repeated. When the timeout period comes to an end ("NO" in the step S8-2), an erasing operation is collectively performed for memory blocks selected as erase object memory blocks in a step S8-5, thereby ending the erasing operation mode.
With the conventional non-volatile semiconductor memory device of FIG. 1, however, there are several problems described below. For instance, the conventional non-volatile semiconductor memory device is not provided with a means for notifying the CPU whether a memory block designated by the CPU as an erase object memory block has been actually selected or not, i.e., whether the information for indicating the memory block selected by the block decoder 4 as an erase object memory block has been latched by the corresponding block latch circuit or not. Because of this, the CPU needs to perform an operation shown in FIG. 4 so as to check whether a memory block designated as an erase object memory block has been actually selected in the conventional non-volatile semiconductor memory device. As shown in FIG. 4, after the erasing operation in the non-volatile semiconductor memory device of FIG. 1, the CPU reads all the addresses in all memory blocks designated as erase object memory blocks in a step S8-6, so as to judge whether all the data is "1" or not in a step S8-7. If there is a memory block which has not been selected as an erase object memory block due to noise or the like, the CPU performs a memory block address and erase command writing operation for the memory block, so that the non-volatile semiconductor memory device of FIG. 1 performs another erasing operation. These processes result in a considerably long erasing operation time.